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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:56:54 09/26/2013 
-- Design Name: 
-- Module Name:    adder_5op - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity adder_5op is
	port( a1, a2, a3, a4, a5 : in STD_LOGIC_VECTOR(63 downto 0);
			result : out STD_LOGIC_VECTOR(63 downto 0));
end adder_5op;

architecture Behavioral of adder_5op is
	component carry_save_adder is
		port(	a : in STD_LOGIC_VECTOR(63 downto 0);
				b : in STD_LOGIC_VECTOR(63 downto 0);
				c : in STD_LOGIC_VECTOR(63 downto 0);
				carry : out STD_LOGIC_VECTOR(63 downto 0);
				partialSum : out STD_LOGIC_VECTOR(63 downto 0));
	end component;
	component adder_64 is
		port(	a, b : in STD_LOGIC_VECTOR(63 downto 0);
				sum : out STD_LOGIC_VECTOR(63 downto 0));
	end component;
	
	signal c1, s1, c2, s2, c3, s3 : STD_LOGIC_VECTOR(63 downto 0) := X"0000000000000000";
	
begin
	csa1 : carry_save_adder port map (a1, a2, a3, c1, s1);
	csa2 : carry_save_adder port map (c1, s1, a4, c2, s2);
	csa3 : carry_save_adder port map (c2, s2, a5, c3, s3);
	adder1 : adder_64 port map (c3, s3, result);

end Behavioral;

